1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system including the memory device.
2. Description of the Related Art
A computing system uses a memory device, such as dynamic random access memory (DRAM), in order to store data accessed by a central processing unit (CPU) or a processor. A computing system requires higher performance the technologies develop. To this end, memory devices are subject to higher density integration and higher speed. In order to increase operating speed of a memory device, various methods for efficiently driving circuits included in the memory device are being discussed in addition to a method of increasing the frequency of a clock at which the memory device operates.
A memory device may include a plurality of memory banks. Referring to FIG. 1, a memory device may include a plurality of memory banks BK0-BK15, a signal input/output (I/O) circuit 110, and a global bus GIO_BUS.
The memory banks BK0-BK15 may be identified by bank addresses based on a single storage unit that includes a plurality of memory cells. The memory device may receive command signals and addresses applied thereto and may input and output data through the signal I/O circuit 110. The global bus GIO_BUS may transfer data between the memory banks BK0-BK15 and the data I/O circuit 110.
A method for alternately accessing the plurality of memory banks BK0-BK15 may be used as a method for increasing the bandwidth of the memory device. For example, while a memory bank BK0 is activated and data is inputted and outputted, another memory bank BK3 may be activated, thereby consecutively inputting and outputting data of the plurality of memory banks BK0-BK15. In this case, an interval of tRRD (Row address strobe to Row address strobe Delay) is required between active commands applied for the two active operations. Such tRRD is defined in the specification and may be commonly set to be longer than tRCD (Row address strobe to Column address strobe Delay) or tCCD (Column address strobe to Column address strobe Delay).
In general, if a single memory bank is to be activated, a single selected word line is activated and memory cells connected to the activated word line are accessed. During this operation, the remaining word lines of the same memory bank may maintain an inactive state. It may be difficult to increase the bandwidth of a memory device or efficiently drive the memory device through such control of the memory bank.